This application relates to maintaining threshold stability when switching transistors at high frequencies, and more specifically to maintaining threshold stability of comparators having transient variations of its transistor parameters.
The physical limitations of the conventional silicon dioxide as a gate dielectric in transistors have reached the point where dioxide films thicknesses are only a few atomic layers thick. Below the physical thickness of 15 A, the gate leakage current exceeds the specifications (e.g. 1 A/cm2). To overcome this critical problem, highly resistive dielectrics have been introduced into the transistor as hafnium-based, zirconium, aluminum oxides. In fact, while keeping the equivalent oxide thickness constant, highly resistant dielectrics allow increasing in the physical thickness of the transistor's gate stack. Hence gate leakage is reduced by 2 to 3 orders of magnitude. Although a large amount of effort has been invested toward highly resistive gate dielectrics, many critical problems still remain.
One of the challenges for the integration of highly resistive dielectrics is maintaining the transistors threshold voltage stability during operation. In addition to static mismatch transient variation come, transient variations of transistor parameters (e.g. VT, μ . . . ) in advanced CMOS technologies are caused by effects such as charge trapping, self heating or floating body effects. These effects appear when switching electronic devices using the advance CMOS technologies at high frequencies. In addition, well known static mismatch effects can appear and can degrade the performance of mixed-signal circuits significantly.
Voltage or current comparators contain these transient variations. If the comparator is overdriven at its input, the threshold on the gate to trigger the transistor of a differential input pair is shifted asymmetrically. When one transistor of the pair of transistors receives a higher gate to source voltage than the other, a time dependent offset is introduced. If the comparator is no longer being overdriven and provides input voltages closer to its original threshold levels (the level where the threshold of the transistor pair are equal), a threshold offset voltage of several mV appears at this input stage. This offset voltage may be due to the transient variations of the transistor's parameters. This threshold offset voltage decreases with time constants in the range of μs. The accuracy of an analog to digital converter which is using such a comparator is limited to this several mV offset.
Shown in FIG. 1 is a comparator 100 used to detect zero voltage crossings of a signal. Comparator 100 includes comparator circuits 101 and 102. Circuits 101 and 102 include transistors 103 and 104, coupled via load 106 and 108 and via sample and hold circuit 110 to output terminals 112 and 114. Transistors 103 and 104 include source terminals 116 and 118, gate terminals 120 and 122 and drain terminals 124 and 126, respectively. Source terminals 116 and 118 are connected to load 106 and 108, respectively. Gate terminals 120 and 122 are connected to input terminals 130 and 132, and the input terminals receive a respective input signal. The drain terminals 124 and 126 are connected to current source 136. Upon receiving an input signal having a level to saturate gate terminals 120 or 122, transistors 103 and 104 respectively pass current from current source 136 via load 106 and 108 to sample and hold circuit 110. Sample and hold circuit 110 receives a clock signal (designated as “fClock”) on line 140 to hold its output at fixed voltage level for the duration of an fClock period.
Normally the accuracy of the comparator is only needed near the zero voltage crossing (across the gate and drain terminal) or transistor bias level. In certain analog to digital converters, for example, the conversion is done in a successive way. First, a rough estimation of the analog voltage level which has to be converted to a digital signal is done at a first stage of a conversion cycle.
This estimation is then elaborated step by step. Only errors at the last stage of the conversion cycle affect the result. This results in a comparator which can have large errors at the beginning of the conversion cycle and no errors at the last conversion cycle. But due to the transient variations of transistor parameters caused by the overdrive at the first conversion cycle, the error only disappears at the last cycle if the conversion speed is much less than the time constant of this transient variations of transistor parameters.